1. Field of the Invention
The present invention relates to a signal processing circuit of a disc reproduction apparatus such as a disc player which plays a disc on which information is recorded (hereinafter, simply referred to as a "disc") such as a digital audio disc referred to as a "compact disc" (CD) or "mini-disc" (MD), more particularly relates to a signal processing circuit of a disc reproduction apparatus which produces a reproduction clock in synchronization with a reproduced signal from the disc and performs signal processing with respect to the reproduced signal based on this reproduction clock.
2. Description of the Related Art
In a digital audio disc, for example, a disc of a compact disc system, a modulation system referred to as "eight-to-fourteen modulation" (EFM) has been adopted. When demodulating this eight-to-fourteen signal, a clock (hereinafter, simply referred to as a reproduction clock) is produced based on a binary pulse string signal obtained by waveform-shaping an RF signal read from the disc. The demodulation is carried out by using this reproduction clock. For the production of this reproduction clock, generally a phase-locked loop (PLL) circuit has been used.
A conventional example of the phase-locked loop circuit used for the production of this reproduction clock is shown in FIG. 1. In FIG. 1, the oscillation frequency of a crystal oscillator 41 is divided by M (M being an integer) by a prescalar 42. The result becomes one input of a phase comparator 43. The phase comparator 43 receives as its other input a frequency signal obtained by frequency--dividing the oscillation frequency of a voltage-controlled oscillator (VCO) 44 by N (N being an integer) by a prescalar 45, compares the phases of the two frequency signals, and outputs a phase difference signal thereof. This phase difference signal passes through a low-pass filter (LPF) 46 and becomes the control voltage of the voltage-controlled oscillator 44. The voltage-controlled oscillator 44 changes in its oscillation frequency in accordance with this control voltage. The oscillation output of this voltage-controlled oscillator 44 is derived as the reference clock comprising a multiple of L (integer) of the reproduction clock PLLCK which is finally obtained and, at the same time, passes through the prescalar 45 and becomes the other input of the phase comparator 43.
In the above-described circuit structure, the circuit operates so that the phases of the two input signals of the phase comparator 43 coincide and, as a result, the frequencies of the two input signals coincide. Here, as one example, when assuming that the oscillation frequency of the crystal oscillator 41 is 16.9344 MHz, M=24, and N=49, the following relationship stands: Namely, from EQU (PLLCK.times.L)/N=16.9344 MHz/M
one obtains: ##EQU1##
Note that if the frequency of this reproduction clock PLLCK is 4.3218 MHz, this becomes: EQU 34.5744 MHz=4.3218 MHz.times.8
Namely, L becomes equal to 8. Here, when assuming that the sampling frequency fs is the same frequency as that of the compact disc system, that is, 44.1 kHz, 16.9344 MHz becomes 384.times.fs. Further, 4.3218 MHz is a channel clock frequency when PWM-modulating the eight-to-fourteen signal by the compact disc system. The eight-to-fourteen signal is PWM-modulated in steps of one cycle from this 3 cycle to 11 cycle. 34.5744 MHz is a frequency 8 times that of this channel clock.
A reference clock having a frequency 8 times that of this channel clock is given to a digital phase-locked loop circuit 52. This digital phase-locked loop circuit 52 comprises a frequency error counting circuit 47, a low-pass filter 48, a phase error counting circuit 49, an adder 50, and a digital voltage-controlled oscillator 51 and has such a configuration that produces the reproduction clock PLLCK based on the reference clock and, at the same time, detects the frequency error and phase error of the eight-to-fourteen signal with respect to this reproduction clock PLLCK and controls the frequency and phase of the reproduction clock PLLCK based on that frequency error and phase error. Here, the eight-to-fourteen signal is a signal obtained by having the RF signal read from the disc waveform-shaped and digitalized. This binary signal is a signal changing at nT (wherein, n is an integer of from 3 to 11) where the cycle of the channel clock is T.
In the conventional phase-locked loop circuit of the above-described configuration, the system has been designed so that a target rotational speed of the spindle is established according to the crystal precision and, at the same time, the actual rotational speed of the spindle is counted, and a servo loop is formed bringing the difference between this and the target rotational speed to 0, while the center frequency of the phase-locked loop is set in accordance with the eight-to-fourteen signal where the spindle rotates at the target rotational speed, and the phase-locked loop is made able to be normally phase-locked within a frequency range of .+-.f (capture/phase-lock range) with this frequency as the center.
Here, an explanation will be made of the capture/phase-lock range of the phase-locked loop circuit based on the graph of FIG. 2. When the rotation is raised from a state where the spindle rotational speed is slower than the target rotational speed, the input frequency of the phase-locked loop is rising, and therefore the operation point moves to right in FIG. 2. When the frequency indicated by C.sub.- is reached, it suddenly phase-locks, and when the rotation is further raised, the phase-lock is held up to the L.sub.+ point and when the rotation becomes faster than this, the phase-lock is released. When the rotation is lowered from this state, the characteristic is exhibited that a sudden phase-lock occurs at C.sub.+, and the phase-lock is held up to L.sub.-,
This frequency range from L.sub.- to L.sub.+ is referred to as the "phase-lock range" and is determined by the gain possessed by the phase-locked loop. On the other hand, the frequency range from C.sub.- to C.sub.+ is referred to as the "capture range" and always becomes narrower than the phase-lock range. The wider this capture/phase-lock range .+-.f, the better, but in a conventional phase-locked loop circuit, there was a frequency displacement of about 5 percent. This was because, for example, in the signal of 11 T and 10 T, where an eight-to-fourteen signal of 10.5 T which is deviated by 5 percent is input, it becomes impossible to correctly determine whether the period of 10 T becomes longer or the period of 11 T becomes shorter.
As mentioned above, in a conventional phase-locked loop circuit, the rotational speed of the spindle is constantly controlled so as to become the target speed. When it is set at this speed, the phase-locked loop may be phase-locked to enable the data to be normally reproduced. Note, since the actual rotational speed of the spindle deviates from the target value, to make up for this amount of deviation, as mentioned above, a certain degree of a capture/phase-lock range .+-.f of the phase-locked loop had become necessary.
However, for example, in a state where a compact disc player is used outdoors, where the player unit is rotated in the direction of rotation of the disc or in a direction opposite to the rotation thereof, the relative speed with respect to the pick-up deviates to a large extent due to the inertia of the spindle, whereby the rotational speed of the spindle deviates by a large extent from the target speed and the signal is no longer within the capture/phase-lock range .+-.f. Therefore, there were the problems that the player was susceptible to rotational outer disturbances, for example, the phase-lock of the phase-locked loop was released and the music ceased, and was poor in high speed access.